1、三个常见的for循环C语言代码如下：

#include "stdio.h"
typedef unsigned int u32 ;
typedef unsigned char u8;
void main()
{

    u32 data = 0;
    u32 data1 = 0;
    u32 data2 = 0;
    u32 i = 0,j = 0;
//------------------------------1----------------------
    for(i=0;i<100;i++)
    {
        data = data + 100;
    }
    printf("data = %d\n",data);

//------------------------------2----------------------
    for(i=0;i<100;i++)
     {
         data1 = data1 + i;
     }   
    printf("data1 = %d\n",data1);

//------------------------------3----------------------
    for(i=0;i<100;i++)
     {
        for(j=0;j<10;j++)
        {
            data2 = data2 + j;
        }
     }
    printf("data2 = %d\n",data2);

}

程序运行结果如下：

2.Verilog代码的实现方法：

verilog的代码实现 for_while.v如下:

module for_while(clk,rst_n,ntimes,data,data1,data2);
input clk;             //
input rst_n;           //
input [31:0]ntimes;
output reg [31:0] data;
output reg [31:0] data1;
output reg [31:0] data2;
wire [31:0] N;
assign N = ntimes;//the ntimes is set to 100 for modelsim sumulation
//assign N = 100;
reg [7:0] state;
reg [31:0] i;
reg [31:0] j;

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
    begin
        data <= 0;data1 <= 0;data2 <= 0;
        state <= 0;
        i <= 0;
        j <= 0;
    end
else
    begin
        case(state)
     //步骤8'd0中，实现第1种for循环  
        8'd0://this state is for the for_while function:   and the i is like the i in for_while.c
            begin
            if(i == N ) //if you want N times,i is recording the times
                begin
                    i <= 0;
                    state <= state + 1;
                   
                end
            else
                begin
                    i <= i + 1;
                    data <= data +100;           
                end
            end                    //total time 50MHZ  2us

      //步骤8'd1中，实现第2种for循环 
        8'd1:  //100times 2us
            begin       
                if(i == N ) //if you want N times,i is record the times
                    begin
                        i <= 0;
                        state <= state + 1;
                       
                    end
                else
                    begin
                        i <= i + 1;
                        data1 <= data1 + i;           
                    end
            end

      //步骤8'd2中，实现第3种for循环 
        8'd2:  //100*10 times total time 25us
            begin       
                if(i == N ) //if you want N times,i is record the times
                    begin
                        i <= 0;
                        state <= state + 1;
                       
                    end
                else
                    begin
                       
                        if(j == 10)
                            begin
                                i <= i + 1;
                                j <= 0;
                            end
                        else
                            begin
                                data2 <= data2 + j;
                                j <= j + 1;
                            end
           
                    end
            end       
        endcase
    end
end
endmodule

verilog的代码实现 仿真程序如下:

`timescale 1 ns/ 1 ps
module fpga_models_vlg_tst();
reg clk10;
reg rst_n;

                     
fpga_models i1 (
    .clk10(clk10),
    .rst_n(rst_n)
);
initial                                               
begin                                                 
                                        
$display("Running testbench");                      
end 

initial begin
clk10 = 0;
rst_n = 0;

#100;
rst_n = 1;

end

always #50 clk10 = ~clk10;

wire clk50;
clk_pll u0
    (
    .inclk0(clk10),
    .c0(clk50)
    );

wire  [31:0]data;
wire [31:0]data1;
wire [31:0]data2;
for_while for_while_1
(
    .clk(clk50),
    .rst_n(rst_n),
    .ntimes(100),
    .data(data),
    .data1(data1),
    .data2(data2)
);

运行结果与C语言程序完全一样，达到循环效果：