加载中…spinalHDL中blackBox时钟map映射
(2018-01-17 10:32:16)
标签：
spinalhdlverilogdomainscalaram |
分类： spinalHDL |
以定义一个xilinx中的Ram为例，定义的Mem_Ram相当于一个黑盒，port端口与xilinx IP 中的Ram映射。
val io = new Bundle{
val clk = in Bool
val reset = in
Bool
val en = in Bool
val wr = in Bool
val addr = in UInt(5
bits)
val wrdata = in UInt(9
bits)
val rdata = out UInt(9
bits)
}
mapCurrentClockDomain(io.clk,io.reset)
val io = new Bundle {
val
en = in Bool
val
wr = in Bool
val
addr = in UInt (log2Up(32) bit)
val
wrdata = in UInt (9 bit)
val
rdata = out UInt(9 bits)
}
//Instantiate the blackbox
val ram = new Mem_Ram
//Interconnect all that stuff
io.en <>
ram.io.en
io.wr <>
ram.io.wr
io.addr <> ram.io.addr
io.wrdata <> ram.io.wrdata
io.rdata <>
ram.io.rdata
def main(args: Array[String]): Unit =
{
SpinalVerilog(new
TopLevel)
}
input io_en,
input io_wr,
input [4:0]
io_addr,
input [8:0]
io_wrdata,
output [8:0] io_rdata,
input reset,
input
clk
Mem_Ram ram (
.io_clk(clk),
.io_reset(reset),
.io_en(io_en),
.io_wr(io_wr),
.io_addr(io_addr),
.io_wrdata(io_wrdata),
.io_rdata(io_rdata)
);
MyRam dut
(
.clka(io_clk),
.rsta(io_reset),
.ena(io_en),
.wea(io_wr),
.addra(io_addr),
.dina(io_wrdata),
.douta(io_rdata)
);
.scala中的时钟和复位有两种表示方式，第一种：Map
the current clock domain to the io.clk pin，current reset to the
io.reset pin
val io = new Bundle{
val clk = in Bool
val reset = in
Bool
val en = in Bool
val wr = in Bool
val addr = in UInt(5
bits)
val wrdata = in UInt(9
bits)
val rdata = out UInt(9
bits)
}
mapClockDomain(clock
= io.clk,reset = io.reset)
class Mem_Ram extends BlackBox{
}
第二种：Clock
and reset is map on the current clock domain
class Mem_Ram extends BlackBox{
}
在Component中例化BlackBox。如下：
// Create the top level and instantiate the Ram
class TopLevel extends Component {
}
object Main {
}
生成的.v文件如下：
module TopLevel
(
);
endmodule
在vivado中例化一个xilinx的RamIP，模块名称为MyRam。
完成后，再编写一个Mem_ram.v文件，将BlackBox Mem_ram和MyRam映射好。
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