一个verilog配置引脚的范本
(2013-01-11 17:44:11)
标签:
杂谈 |
分类: FPGA |
#------------------GLOBAL--------------------#
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT
TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
#复位引脚
set_location_assignment
#时钟引脚
set_location_assignment
#数码管对应的引脚
set_location_assignment
set_location_assignment
set_location_assignment
set_location_assignment
set_location_assignment
set_location_assignment
set_location_assignment
set_location_assignment
set_location_assignment
set_location_assignment
存成.tcl 文件在quartus里面运行就OK了