（1）ERROR:NgdBuild:770 - IBUFG 'instance_name/clkin1_buf' and BUFG
   '_i000006/clkout1_buf' on net 'clk_rx' are lined up in series. Buffers of the
   same direction cannot be placed in series.

ERROR:NgdBuild:924 - input pad net 'clk_rx' is driving non-buffer primitives:

解决：

（2）ERROR:NgdBuild:455 - logical net 'clk_tx' has multiple drivers

解决：这两个错误出现好像是和IBUFG有关，按照别人的方法，我把第二个dcm模块中的IBUFG给去掉了，然后这两个错误就没有了。原因就是IBUFG的输入只能是全局时钟，而第一个dcm的输出信号是作为内部信号连接到第二个dcm模块的，所以就不需要IBUFG了。（已证实）

If multiple IBUF (and OBUF) type components are connected in series, NGDBuild reports the errors as listed above. Examples of IBUF-type components that should not be connected together include the following:

IBUFx
IFDDRx
BUFG

比如一个DLL输出的时钟信号不能赋给另一个DLL作为输入信号。

 

（3） Processing TIMESPEC TS_ce_16_80251d7c_group_to_ce_16_80251d7c_group: user TIMEGRP 'ce_16_80251d7c_group' must be

previously defined in FROM/TO constraint.

解决： I think that System Generator somehow thought that there were two clock domains in the FPGA portion of the design (even though there was only one) and created the unused constraint, which was throwing off the Xilinx synthesis tool. I've only just started using System Generator, so maybe this is not the right explanation, but the error is gone, and I can compile. :)

就是说getin端口有不同的时钟输入，仔细检查