上升沿：

                module risetest(in,clk,out); 
                 input in,clk; 
                 output out; 
                reg q1,q2; 
                 always@(posedge clk) 
                     q1<=in;      

                  always@(posedge clk) 
                     q2<=q1; 
                assign   q3=!q2; 
                assign   out=q1&&q3; 
    endmodule

综合电路图

http://filer.blogbus.com/5863294/586329412727226231.jpg

状态机实现：

                 module   risetest(in,clk,out);
                              input in,clk;
                              output out;
                              reg[1:0] state;
                              parameter  S0=2'b00,
                                              S1=2'b01,
                                              S2=2'b11;
                            always@(posedge clk)
                                    begin
                                     state<=S0;
                                   case(state)
                                       S0:
                                             if(in)
                                              state<=S1;
                                             else
                                              state<=S0;
                                      S1:  
                                             if(in)
                                              state<=S2;
                                             else
                                              state<=S0;
                                      S2: 
                                             if(in)
                                               state<=S2;
                                            else
                                                state<=S0;
                                         default: state<=S0;
                                     endcase
                                 end
                              assign  out=state[1]^state[0];           
        endmodule

测试代码：

                        module risetest_tb;
                                   reg clk,in;
                                 initial
                                   begin
                                   $dumpfile("clk.vcd");
                                   $dumpvars;
                                  end
                            risetest inst(
                                              .in(in),
                                              .clk(clk),
                                              .out(out));
                                 initial
                                       forever #5 clk=~clk;
                                 initial
                                         begin
                                             clk=0;in=0;
                                      #40  in=1;
                                      #80  in=0;
                                      #30  $finish;
                                         end
endmodule
仿真波形：

http://filer.blogbus.com/5863294/58632941273198048c.jpg

测试正确。
总结：状态机实现时用的器件比第一种实现方法使用的器件多，第一种方法是你的数电的功底（所谓的看代码知硬件^_^），能用很简单的方法实现，状态机适合在比较复杂的电路设计。

下降沿检测：

              module falltest(in,clk,out); 
                  input in,clk; 
                 output out; 
                  reg q1,q2; 
        always@(posedge clk) 
                  q1<=in;      

        always@(posedge clk) 
                q2<=q1; 
    assign   q3=!q1; 
    assign   out=q2&&q3; 
    endmodule

综合电路图

http://filer.blogbus.com/5863294/586329412727226414.jpg

双沿检测：

              module frtest(in,clk,out); 
                    input in,clk; 
                   output out; 
                   reg q1,q2; 
          always@(posedge clk) 
                     q1<=in;      

          always@(posedge clk) 
                    q2<=q1; 
          assign   out=q2||q1; 
    endmodule

综合电路图

 http://filer.blogbus.com/5863294/58632941272722607p.jpg

小节：这个电路还是有些价值的，当慢时钟域向快时钟域转变时，一般采用2个DFF，这些电路可以检测输入时钟的上升和下降沿，小小考验一下你的数电功底。

这个电路的用处：贴一张图上来就知道了

http://filer.blogbus.com/5863294/58632941273028707g.jpg

                                                 异步时钟同步化

总结：这三种电路都可以用状态机实现，可是都只能在下一个周期才能检测到边沿的变化。