library ieee;
use ieee.std_logic_1164.all;

entity fenpin3 is
port(clock:in std_logic;
      clk:out std_logic);
end;

architecture devider of fenpin3 is
signal counter:integer range 0 to 2;
signal temp1,temp2:std_logic;

begin
process(clock)
begin
if rising_edge(clock) then
    if counter=2 then
     counter<=0;
      temp1<=not temp1;
   else
    counter<=counter+1;
end if;
end if;

if falling_edge(clock) then
   if counter=1 then
    temp2<=not temp2;
end if;
end if;
end process;
clk<=temp1 xor temp2;
end;