十点一分频的verilog代码

转自：http://blog.sina.com.cn/s/blog_4de3f3d201000bcx.html

最近在学fpga,学到关于小数分频的部分,查阅相关的资料,写了一个10.1分频的程序,经modelsim验证时序正确,写出来以飨大家.因为是新手,纰漏之处在所难免,欢迎大家批评指正.

(本段是从网上拷贝)小数分频的基本原理是采用脉冲吞吐计数器和锁相环技术先设计两个不同分频比的整数分频器，然后通过控制单位时间内两种分频比出现的不同次数来获得所需要的小数分频值。如设计一个分频系数为10.1的分频器时，可以将分频器设计成9次10分频，1次11分频，这样总的分频值为：

F=（9×10+1×11）/（9+1）=10.1

10.1分频的正确代码
module ten_point_one_div(
                          input clk_in,        //input clk;
                          input rst_n,         //asynchronous reset signal
                          output reg clk_out,  //output clk;
                         );
reg [3:0] clk_10_times;                        //counter the times of ten cycles
reg [3:0] counter;                             // a interior counter
always@(posedge clk_in or negedge rst_n)
begin
    if(!rst_n)                                 //reset
        begin
          clk_10_times<=0;
          clk_out<=0;
          counter<=0;
        end
    else if(clk_10_times<9)                    //counter 90 clock_in cycles
          begin
             if(counter<4'b1001)
               begin
                counter<=counter+4'b0001;
                clk_out <=0;
              end
             else
               begin
                 counter<=0;
                 clk_out <=1;
                clk_10_times<=clk_10_times+1;
               end
          end
      else                                      //counter 11 clock_in cycles         
     begin
        if(counter<4'b1010)
          begin
              counter<=counter+4'b0001;
              clk_out <=0;
           end
         else
              begin
                  counter<=0;
                  clk_out <=1;
                  clk_10_times<=0;       //prepare for the next turn
               end
      end  
end        
endmodule
module test_ten_point_one_div;
      reg clk_in;
      reg rst_n;
      reg [3:0]clk_10_times;
      reg [3:0]counter;
      always #5 clk_in=~clk_in;
      initial
      begin
       clk_in=0;
       rst_n=0;
       counter=0;
       clk_10_times=0;
       #10 rst_n=1;
      end
    ten_point_one_div u(.clk_in(clk_in),
             .rst_n(rst_n),
             .clk_out(clk_out)
                          );
endmodule