加载中…调用74系列的原理图生成HDL文件进行modelsim仿真遇到的问题
(2011-11-22 14:31:31)
标签：
进行74系列d70端口库文件 |
分类： iFPGA |
问题1：将子原理图如counter8.bdf转化为.bsf文件时提示
Can't open read-only file counter8.bsf
altera官网的解释如下：
Title
Can't open read-only file <module>.bsf
Description
Due to a problem in the Quartus® II software version 11.0, you may see this error when trying to generate a Block Symbol File (.bsf) from a Block Design File (.bdf). This error occurs when the .bsf does not currently exist or the .bsf exists but does not have write permission for all users.
To work around this problem, create an empty file named
<module>.bsf
and ensure that it has write permission for all users. Then, open
the .bdf in the Quartus II software and generate
the symbol file using the name of the empty
.bsf.
This problem is scheduled to be fixed in a future release of the Quartus II software.
即新建一个空的.bsf文件，命名为counter8.bsf存档为工程目录下，然后再执行creat
//////////////////////////////////////////////////////////////////////////////////
问题2：在quartus ii中调用modelsim进行RTL仿真，设置完毕之后执行，提示出现错误，请查看nativelink相关文件，打开nativelink_simulation
Info: Start Nativelink Simulation process
Error: NativeLink did not detect any HDL
files in the project
Error: NativeLink simulation flow
was NOT successful
================The following additional information is provided
to help identify the cause of error while running nativelink
scripts=================
Nativelink TCL script failed with errorCode:
Nativelink TCL script failed with errorInfo:
"if ![qmap_successfully_completed] {
"run_eda_simulation_tool eda_opts_hash"
即没有找到HDL文件，才想起modelsim是使用.v文件进行仿真的，于是将顶层fre.bdf转换为fre.v，此时再进行调用，又出现同样问题，在quartus
ii编译一下，提示出现duplicated，即重复定义了，将fre.bdf移除工程外，再次编译通过，调用modelsim成功。（或者在外部用fre.v和testbench进行仿真）
再次打开nativelink文件
Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog
design -- Verilog simulation models will be used
========= EDA Simulation Settings =====================
Sim
Mode
Family
Quartus
root
Quartus sim
root
Simulation
Tool
Simulation Language
Simulation
Mode
Sim Output
File
Sim SDF
file
Sim
dir
=======================================================
Info: Starting NativeLink simulation with ModelSim-Altera
software
Sourced NativeLink script
d:/altera/11.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
Info: Spawning ModelSim-Altera Simulation software
///////////////////////////////////////////////////////////////
问题3：modelsim仿真编译不通过，找不到相关元件库。
包括74系列和counter8，tf_ctro都出现 fail.The design unit was not found.
第一想法是是不是modelsim内没有编译相关的库文件，上网查询发现se.pe版本想要添加到库的在ase版本都已经具备。故排除此问题。
查看error提示，发现在搜索路径都没有找到unit说明，自己再在simulation选项中设置其他路径，还是一样找不到，说明很可能这些都不存在已有的库中。为了进行验证，我将tf_ctro.bdf转换为.v加进去仿真，结果关于tf_ctro的错误没有了，但其他错误还在，说明猜测是正确的。
知道是怎样的问题就着手解决，途径有1：直接将74系列和counter8，tf_ctro等.bdf转换为.v加进去modelsim工程下进行仿真。2：建立自己的库，里面添加相关.v进行编译，然后在.ini文件指定路径，仿真时指定库文件即可（网上有关于se编译altera库的教程，类似的过程，不述）。无论哪种方法，都要先生成.v文件才行。
此时又出现了问题。
///////////////////////////////////////////////////////
问题4：一些74系列芯片端口引脚非法命名
在生成counter8.v时出现错误
help解释如下：
Design file contains illegal characters for Verilog HDL
| CAUSE: | You created a name characters. This can cause the Verilog Design File to not compile once it is generated. |
| ACTION: | Rename the pin or port to exclude the illegal name characters and create the HDL design file again. |
想不出是那些字符非法，试着转换为.vhd,也是出现错误，但是更有启发
从中可以看出是74390的端口管脚在HDL语言看来是非法的，
因为verilog端口命名是不能数字开头的，所以提示非法字符。
没办法只能想着能不能将端口名换掉，奈何是只读文件，没有权限去更改啊，本来还奇怪为什么前面的tf_ctro.v能够转换成功，原来里面用到的74154端口命名没有出现数字开头的情况。
没办法只能去google，结果令人失望，相关问题检索出很少，alteraforum的两条也帮助不大，如下：
It's a TTL numerated symbol that maps the old TTL discrete logic circuits.
In order to simulate it I do the following:
1)
"File | Create/update | HDL from current file" to generate the Verilog code of the circuit
2)
Add a Verilog test bench
3)
Remove the .bdf file from the project and add the Verilog version of it.
Now the project is composed by two Verilog files (project and test bench)
After compiling the project (that synthesizes without errors) I can run a gate level simulation. Unfortunately I cannot run an RTL
simulation since I don't have the Verilog file for the 7493 component.
What I can do in order to run both RTL and gate level simulations for a project that uses these kind of library components?
Thx.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
reply:
if you go to $QUARTUS_ROOTDIR/libraries/other/maxplus2 you'll
find 7493.bdf. if you open it up you'll see the component's source.
go to File > Create > Create HDL for
current file and create a Verilog file. when you create the .v from
the 7493.bdf in you get the following warning explaining the
slash:
Warning: Design name for "7493" contains a number -- illegal for
Verilog HDL and VHDL -- adding "\" in front of name
the 7493.v file looks like its just HDL for the .bdf, it doesn't
instantiate any other components. add the file to your project, and
Quartus should use this instead of the .bdf to compile your design,
which should allow use in ModelSim (i didn't try vsim). if it
doesn't work in ModelSim, rename the module from \7493 to my7493
and rename the instantiation and that should fix it
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
two:
I am new to Altera and would simply like to convert a .bdf file
to .vhd. Using primatives works but specifying generic chips such
as 7404, 7408, 7432, etc seems to have problems because the names
of entities and ports start with a numeral rather than a letter. My
inputs and outputs to the chips begin with a letter in the name but
the chips are defined in the library
.../altera/10.0sp1/quartus/libraries/others/maxplus2/ with only
numbers for the port and entity names. I have used
"File->Create/Update->Create HDL
design file from current file" to convert from bdf to vhd and it
recognizes some of these problems and puts a "\" in front of some
of the names but never any of the ports.
The .bdf and the generated .vhd files are attached
Using the linux version of altera 10.0sp1 on SUSE 11.3
(Linux 2.6.34.7-0.3-desktop x86_64)
Messages from "Create/Update->Create HDL design file
from current file"
#Warning: Found Altera-specific megafunction, primitive or
component "7404" p, li { white-space: pre-wrap;
#Warning: Design name for "7404_0" contains a number -- illegal for
Verilog HDL and VHDL -- adding "\" in front of name
#Error: Name "2" in design file .../testproj2.vhd contains illegal
character for VHDL
#Error: Name "1" in design file .../testproj2.vhd contains illegal
character for VHD#Error: Can't elaborate top-level user
hierarchy
I'm sure there must be a simple fix for this. Grateful for any
advice.
Regards,
jake
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
b2v_inst : 7404
If I leave it as 7404 I get the following error when running "Start Analysis and Elaboration":
#Error (10500): VHDL syntax error at 7404_0.vhd(40) near text "7404"; expecting "(", or an identifier, or a sequential statement
If I change it to \7404\ then I get the error:
#Error (10482): VHDL error at 7404_0.vhd(40): object "7404" is used but not declared
It appears I would have to rename the library function and at that point I knew I was doing something wrong since someone would have already made these changes.
By the way, where is b2v_inst defined?
Thanks much
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
还不能解决问题就去QQ群问咯，结果连大神也不清楚，说实在不行就不要用modelsim仿真了，用内置的得了，但是quartus
ii 10.0以上版本都不带内置simulator了啊，唉就暂时搁置吧，搞了一天了，NND。
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