在Verilog语法中，嵌套的if-else语句可以给出测试条件的优先级，如果想不给出优先级而译码一个值，可以使用case语句。来看下面的一个简单状态机的例子：

Fig1.状态图

实现程序（Verilog）：

module stt(
    output reg gnt,
    input dly, done, req, clk, rst_n);
    parameter [1:0] IDLE = 2'd0,
                          BBUSY = 2'd1,
                          BWAIT = 2'd2,
                          BFREE = 2'd3;

    reg [1:0] state;

    always @(posedge clk or negedge rst_n)
        if (!rst_n) begin
            state <= IDLE;
            gnt <= 1'b0;
        end
        else begin
            state <= 2'bx;
            gnt <= 1'b0;
            case (state)
                IDLE : if (req) begin
                            state <= BBUSY;
                            gnt <= 1'b1;
                        end
                        else state <= IDLE;
                BBUSY: if (!done) begin
                            state <= BBUSY;
                            gnt <= 1'b1;
                        end
                        else if ( dly) begin
                            state <= BWAIT;
                            gnt <= 1'b1;
                        end
                        else state <= BFREE;
                BWAIT: if ( dly) begin
                              state <= BWAIT;
                              gnt <= 1'b1;
                        end
                        else state <= BFREE;
                BFREE: if (req) begin
                            state <= BBUSY;
                            gnt <= 1'b1;
                        end
                        else state <= IDLE;
            endcase
        end
endmodule

拿程序中的BBUSY状态为例，它包含三种输出状态：BBUSY，BFREE，BWAIT，状态图中表明的转移条件为BBUSY->BBUSY(!done),BBUSY->BWAIT(dly && done),BBUSY->BFREE(!dly && done)，实现描述语言如下：

                        BBUSY: if (!done) begin
                            state <= BBUSY;
                            gnt <= 1'b1;
                        end
                        else if ( dly) begin
                            state <= BWAIT;
                            gnt <= 1'b1;
                        end
                        else state <= BFREE;

done与！done，dly与！dly都是互斥的条件，所以可以在条件列表中省略这些描述，QuartusII编译器在编译时会自动添加这些条件，此程式的编译结果如下：