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DDR引脚信号定义

(2012-07-29 23:30:29)
标签：

杂谈
DDR原理图如下所示：

 

 

DDR引脚的具体功能如下表：

 

 
 
 PIN NUMBERS    SYMBOL    TYPE    DESCRIPTION  
10  Reset#    Input   Asynchronously forces all registered ouputs LOW when RESET#  is LOW. This signal can be used during power-up to ensure CKE  is LOW and DQs are High-Z.  
 63, 65, 154    WE#, CAS#, RAS#    Input   Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.    
 137, 138    CK0, CK0#    Input   Clock: CK, CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive  edge of CK,and negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#.     
 21,111    CKE0, CKE1    Input   Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE)  are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied.            
 157, 158    S0#, S1#    Input   Chip Selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code.       
 52, 59    BA0, BA1    Input   Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied.   
 27, 29, 32, 37, 41, 43, 48,  115 (512MB, 1GB), 118,  122, 125, 130, 141    A0-A11 (256MB) A0-A12 (512MB, 1GB)     Input   Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command.          
 97, 107, 119, 129, 140, 149, 159, 169, 177     DM0-DM8    Input   Data Write Mask: DM LOW allows WRITE operation. DM HIGH blocks WRITE operation. DM state does not affect READ command.   
 5, 14, 25, 36, 47, 56, 67, 78, 86     DQS0-DQS8    Input/ Output   Data Strobe: Output with READ data, input with WRITE data. DQS is edge-aligned with READ data, centered in WRITE data.  Used to capture data.  
 44, 45, 49, 51, 134, 135, 142, 144     CB0-CB7    Input/ Output   Check Bits: ECC, 1-bit error detection and correction.  
2, 4, 6, 8, 12,13, 19, 20,23, 24, 28, 31, 33, 35, 39,40, 53, 55, 57, 60, 61, 64,68, 69, 72, 73, 79, 80, 83,84, 87, 88, 94, 95, 98, 99,105, 106, 109, 110, 114,117, 121, 123, 126, 127,131, 133, 146, 147, 150,151, 153, 155, 161, 162,165, 166, 170, 171, 174,175, 178, 179 DQ0-DQ63 Input/Output Data I/Os: Data bus.
92 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module.
181182183 SA0-SA2 input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device.
91 SDA Input/Output Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module.
1 Vref Input SSTL_2 reference voltage.
15, 22, 30, 54, 62, 77, 96,104, 112, 128, 136, 143,156, 164, 172, 180 VDDQ Supply DQ Power Supply: +2.5V ±0.2V.
7, 38, 46, 70, 85, 108, 120,148, 168 VDD Supply Power Supply: +2.5V ±0.2V.
3, 11, 18, 26, 34, 42, 50,58, 66, 74, 81, 89, 93, 100,116, 124, 132, 139, 145,152, 160, 176 Vss Supply Ground
184 Vddspd Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
16, 17, 75, 76, 90 DNU —— Do Not Use: Thes pins are not connected on these modules, but
are assigned pins on other modules in this product family.
9, 71, 82, 101, 102, 103,113, 115 (256MB), 163,167, 173 NC No Connect: These pins should be left unconnected.

 

 

 

内存颗粒


                             x8       x16                                   x16      x8

                             VDD      VDD      1                     66     VSS     VSS
                             DQ0      DQ0      2                     65     DQ15     DQ7
                            VDDQ     VDDQ      3                     64     VSSQ    VSSQ
                              NC      DQ1      4                     63     DQ14     NC
                             DQ1      DQ2      5                     62     DQ13     DQ6
                            VSSQ     VSSQ      6                     61     VDDQ    VDDQ
                              NC      DQ3      7                     60     DQ12     NC
                             DQ2      DQ4      8                     59     DQ11     DQ5
                            VDDQ     VDDQ      9                     58     VSSQ    VSSQ
                              NC      DQ5     10                     57     DQ10     NC
                             DQ3      DQ6     11                     56     DQ9      DQ4
                            VSSQ     VSSQ     12                     55     VDDQ    VDDQ
                              NC      DQ7     13                     54     DQ8      NC
                              NC       NC     14                     53     NC       NC
                            VDDQ     VDDQ     15    400mil X 875mil  52     VSSQ    VSSQ
                              NC     LDQS     16                     51     UDQS     DQS
                              NC       NC     17     66pin TSOP -II  50     NC       NC

                             VDD      VDD     18    0.65mm pin pitch 49     VREF    VREF
                              NC       NC     19                     48     VSS     VSS
                              NC      LDM     20      (Lead free)    47     UDM      DM
                              /WE     /WE     21                     46     /CK     /CK
                             /CAS    /CAS     22                     45     CK       CK
                             /RAS    /RAS     23                     44     CKE      CKE
                              /CS      /CS    24                     43     NC       NC
                              NC       NC     25                     42     A12     A12
                             BA0      BA0     26                     41     A11     A11
                             BA1      BA1     27                     40     A9      A9
                           A10/AP  A10/AP     28                     39     A8      A8
                               A0      A0     29                     38     A7      A7
                               A1      A1     30                     37     A6      A6
                               A2      A2     31                     36     A5      A5
                               A3      A3     32                     35     A4      A4
                             VDD      VDD     33                     34     VSS     VSS

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