testbench时钟信号的编写
(2015-12-18 08:48:22)
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testbench时钟信号的编写
'timescale 1ns/1ps //定义 时间单位/时间精度
parameter TIME_PERIOD = 10;
reg clock;
initial
begin
clock = 0;//初始化clock为0
forever
end
parameter TIME_PERIOD = 10;
reg clock;
initial
clock = 0;//初始化clock为0
always
# (TIME_PERIOD/2) clock = ~clock;
parameter HI_TIME = 5,
reg clock;
always
begin
# HI_TIME clock = 0;
# LO_TIME clock = 1;
end
parameter PULSE_COUNT = 4,
reg clock;
initial
begin
clock = 0;//初始化clock为0
repeat (2*PULSE_COUNT)
end
parameter HI_TIME = 5,
reg
wire derived_clock;
always
begin
# HI_TIME absolute_clock = 0;
# LO_TIME absolute_clock = 1;
end
assign # PHASE_SHIFT derived_clock = absolute_clock;

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