通带截止频率近似3KHz，阻带截止频率近似5KHz

fs = 16e3;    % 采样频率

n  = 0:5119;  % 采样点数

x  = sin(2* pi*1e3/fs* n);            %输入原始信号

b  = firhalfband(18,0.00245,'dev');    % 获得设计的半带滤波器抽头系数

impz(b);                                 % 半带滤波器的冲击响应

h  = mfilt.firdecim(2,b)

figure

y_fi = filter(h,x);

x = double(x);

y = double(y_fi);

y = y/max(abs(y));

stem(n(1:44)/fs,x(1:44),'r');

xlabel('时间（sec）');

ylabel('输入信号');

hold on

figure

stem(n(1:2:44)/fs,y(5:26),'filled');

xlabel('信号值');

ylabel('时间（sec）');

 
http://s10/middle/6840802c48e9c267a8369&690

http://s7/middle/6840802c48e9c27cc7df6&690

设计的半带滤波器抽头系数

0.00560198262150479

0

-0.0162426507322625

0

0.0388224806300773

0

-0.0893345598303821

0

0.312377747310891

0.500000000000000

0.312377747310891

0

-0.0893345598303821

0

0.0388224806300773

0

-0.0162426507322625

0

0.00560198262150479

对抽头系数进行量化并放大至整数倍可以得到如下的结果

h(0) = h(18)  = 0.0056    h[2] = h[16] = -0.0162

h[4] = h[14]  = 0.0388    h[6] = h[12] = -0.0893

h[8] = h[10]  = 0.3124    h[9] = 0.500;

为了便于FPGA的设计，将抽头系数放大至2^14倍数，注意在最后的结果中通过移位操作将结果右移14位，即除以2^14，得到正确结果。

h[0] = h[18] = 92 ， h[2] = h [16] =  -265

h[4] = h[14] = 636   h[6] = h[12] =  -1463

h[8] = h[10] = 5118  h[9] = 8192

Simulink中搭建的半带滤波器模块：http://s16/middle/6840802c48e9c2f15baff&690

示波器显示的结果

http://s10/middle/6840802c48e9c33da5469&690

`timescale 1ns / 1ps

 module HB_filter(clk,reset,data_in,data_out);
 parameter width = 15;
 input clk;
 input reset;
 input[15:0]  data_in;
 output[15:0] data_out;
 
 reg[4:0] cnt;
 reg[4:0] add;
 wire[15:0] A_in;
 reg [15:0] B_in;
 
 reg Load_in,we;
 wire[33:0] P_OUT;
 
 
 always@(posedge clk)begin
  if(!reset)begin
    cnt  <= 0;
  add  <= 0;
  B_in <= 0;
 end
  else begin
    if(cnt == 5'b10100)
    cnt  <= 0;
  else
    cnt  <= cnt + 1;
   end
 
 case(cnt)
    5'b00000 : begin
               add  <= 5'b00000;
       B_in <= 92;
       we   <= 1;
       Load_in <= 1;
       end
      
  5'b00001 : begin
               add  <= 5'b00010;
                   B_in <= -265;
       we   <= 0;
       Load_in <= 0;
       end
      
    5'b00010 : begin
               add  <= 5'b00100;
       B_in <= 636;
       we   <= 0;
       Load_in <= 0;
       end
    5'b00011 : begin
               add  <= 5'b00110;
       B_in <= -1463;
         we   <= 0;
       Load_in <= 0;
       end
    5'b00100 : begin
               add  <= 5'b01000;
       B_in <= 5118;
         we   <= 0;
                   Load_in <= 0;      
       end
  5'b00101 : begin
               add  <= 5'b01001;
       B_in <= 8192;
       we   <= 0;
       Load_in <= 0;
       end
      
    5'b00110 : begin
               add  <= 5'b01010;
       B_in <= 5118;
         we   <= 0;
       Load_in  <= 0;      
       end
      5'b00111 : begin
                   add  <= 5'b01100;
                   B_in <= -1463;
       we   <= 0;
       Load_in  <= 0;                
       end
      5'b01000 : begin
                   add  <= 5'b01110;
                   B_in <= 636;
       we   <= 0;
       Load_in  <= 0;
       end 
     
      5'b01001 : begin
                   add  <= 5'b10000;
                   B_in <= -265;
       we   <= 0;
       Load_in  <= 0;
       end

      5'b01010 : begin
                   add  <= 5'b10010;
                   B_in <= 92;
                   we   <= 0;
       Load_in  <= 0;      
       end
         
  default  : begin
                add   <= 0;
        B_in  <= 0;
        we    <= 0;
        Load_in <= 1;
      end
       endcase
 end
 
  assign data_out[15:0] = reset ? P_OUT[33:18] : 0;
 
  lut16_core lut16_core(
            .a(),
      .spra(add),
      .d(data_in),
      .we(we),
      .clk(clk),
      .spo(A_in)
     
      );
     
  DSP48IP  dsp48(
            .A_IN(A_in),
      .B_IN(B_in),
      .CLK_IN(clk),
      .P_OUT(P_OUT),
      .LOAD_IN(Load_in)   
      );
endmodule