实验课题2  代码转换逻辑电路设计

实验内容：

设计一个代码转换逻辑电路。把7位的ASCII码转换成7段字符显示代码。

能显示字母A，b，C，d，E，F，H，L，o，P，U，Γ，和一些符号(-，_，=，┫，┣，┓，┏)等。

用VHDL语言编程并仿真。

library ieee;
use ieee.std_logic_1164.all;
entity converse is
   port(I_L:in std_logic_vector(0 to 7);
           F_L:out std_logic_vector(0 to 7));
end converse;
architecture behave of converse is
   begin
         case I_L is
              when"1000001"=>F_L<="1110111";
              when"1100010"=>F_L<="0011111";
              when"1000011"=>F_L<="1001110";
              when"1100100"=>F_L<="0111101";
              when"1000101"=>F_L<="1001111";
              when"1000110"=>F_L<="1000111";
              when"1001000"=>F_L<="0110111";
              when"1001100"=>F_L<="0001110";
              when"1101111"=>F_L<="0011101";
              when"1010000"=>F_L<="1100111";
              when"1010101"=>F_L<="0111110";
              when"0000001"=>F_L<="1110000";
              when"0101101"=>F_L<="0000001";
              when"1011111"=>F_L<="0001000";
              when"0111101"=>F_L<="1001000";
              when"0000010"=>F_L<="0110001";
              when"0000011"=>F_L<="0000111";
              when"0000100"=>F_L<="0010001";
              when"0000101"=>F_L<="0000101";
              when others =>F_L<="XXXXXXX";
         end case;
end behave;