【  You enable testbench constructs outside programs with the-ntb_opts dtm compile-time option and keyword argument. The keyword name comes from “dynamic types in modules.”

The testbench constructs that you can enter outside programs with this option are as follows:

classes associative arrays dynamic arrays

SystemVerilog named event  】

根据仿真打印信息，当前使用的VCS版本默认选项里有 -ntb_opts dtm 选项。

实际试验中，Makefile文件的命令选项中定义 -ntb_opts dtm时，会打印如下红线框内的信息：

实际试验结果表明在Makefile文件的命令选项中即使不定义 -ntb_opts dtm选项，也不会报错。

#1 Define MACRO/varible in the top of Makefile

#(1) Define varible UVM_HOME use "=" 

TREE = /proj/sandstone_fe/zhuss/RV_std_for_vcsdebug_1120/

UVM_HOME = $(TREE)/DV_Lab/uvm-1.2

#(2) Define varible VCS_OPTS use "+=", named BianLiang_ZhuiJiaZhi 

VCS_OPTS += -sverilog

VCS_OPTS += -timescale=1ns/1ns

VCS_OPTS += +incdir+$(UVM_HOME)/src

VCS_OPTS += +incdir+$(UVM_HOME)/src/uvm.sv

VCS_OPTS += +incdir+$(UVM_HOME)/src/dpi/uvm_dpi.cc

VCS_OPTS += -l vcs.log

VCS_OPTS += -gui

VCS_OPTS += -R

VCS_OPTS += -ntb_opts dtm

#(3) Source RTL files

RTL_FILES = $(TREE)/DV_Lab/SV_Lab/example/rand_UseClassInModule/rand_UseClassInModule.sv

run:

     vcs $(VCS_OPTS) $(RTL_FILES)

（4）仿真打印信息

http://s5/mw690/001RfU5Bzy73Byxr0Ec74&690module和program的区别" TITLE="sytemverilog(sv)中 module和program的区别" />