今天碰到个错误提示:

"Pin numbers do not match between symbol and component. Run dev_check on device file for more information."
于是找了Run dev_check的方法：

在命令行Command > 输入system 回车，进入DOS模式

输入dev_check device_filename    但始终没有什么发现。

既然是器件pin脚原理图和封装对不上，BGA几百个脚一个个对还是挺费时的，是不是可以从导网表时得到提示呢？

在File-->Import Logic 中重新导入netlist,

http://s16/middle/639b3eb5gadd8cb7ee76f&690Run Dev_check" TITLE="Allegro Run Dev_check" />

点Viewlog，可以发现pin脚错误信息，如下例。

----------------------------------------------------------------------------------------

(---------------------------------------------------------------------)
(                                                                     )
(    Allegro Netrev Import Logic                                      )
(                                                                     )
(    Drawing          : iT.Si691x.AP1x_temp.brd                       )
(    Software Version : 16.3S015                                      )
(    Date/Time        : Mon Sep 26 22:00:07 2011                      )
(                                                                     )
(---------------------------------------------------------------------)

------ Directives ------

RIPUP_ETCH TRUE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'E:/Sis/HW/iT.Si691x.AP1x/V1.0/Allegro';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'E:/SIS/HW/IT.SI691X.AP1X/V1.0/ALLEGRO/iT.Si691x.AP1x_temp.brd';
NEW_BOARD_NAME 'E:/SIS/HW/IT.SI691X.AP1X/V1.0/ALLEGRO/iT.Si691x.AP1x_temp.brd';

CmdLine: netrev -$ -i E:/Sis/HW/iT.Si691x.AP1x/V1.0/Allegro -x -y 1 -z E:/Sis/HW/iT.Si691x.AP1x/V1.0/Allegro/#Taaaaaa02224.tmp

------ Preparing to read pst files ------

Starting to read E:/Sis/HW/iT.Si691x.AP1x/V1.0/Allegro/pstchip.dat
   Finished reading E:/Sis/HW/iT.Si691x.AP1x/V1.0/Allegro/pstchip.dat (00:00:00.12)
Starting to read E:/Sis/HW/iT.Si691x.AP1x/V1.0/Allegro/pstxprt.dat
   Finished reading E:/Sis/HW/iT.Si691x.AP1x/V1.0/Allegro/pstxprt.dat (00:00:00.10)
Starting to read E:/Sis/HW/iT.Si691x.AP1x/V1.0/Allegro/pstxnet.dat
   Finished reading E:/Sis/HW/iT.Si691x.AP1x/V1.0/Allegro/pstxnet.dat (00:00:00.07)

------ Oversights/Warnings/Errors ------

#1   WARNING(SPMHNI-192): Device/Symbol check warning detected.

ERROR(SPMHNI-196): Symbol 'BGA796' for device 'SIS691_2_BGA796_SIS691/SIS685' has extra pin 'T5'.

ERROR(SPMHNI-196): Symbol 'BGA796' for device 'SIS691_2_BGA796_SIS691/SIS685' has extra pin 'T6'.

ERROR(SPMHNI-196): Symbol 'BGA796' for device 'SIS691_2_BGA796_SIS691/SIS685' has extra pin 'T7'.

ERROR(SPMHNI-195): Symbol 'BGA796' for device 'SIS691_2_BGA796_SIS691/SIS685' is missing pin 'T2'.

ERROR(SPMHNI-195): Symbol 'BGA796' for device 'SIS691_2_BGA796_SIS691/SIS685' is missing pin 'T1'.

ERROR(SPMHNI-195): Symbol 'BGA796' for device 'SIS691_2_BGA796_SIS691/SIS685' is missing pin 'T3'.

------ Library Paths ------
MODULEPATH =  E://reuse/modules
           .
           C:/Cadence/SPB_16.3/share/local/pcb/modules
           E:\PSD_Data\CVDLib\AllegroLib\Package16.2\

PSMPATH =  E:\PSD_Data\CVDLib\AllegroLib\Package16.2\

PADPATH =  E:\PSD_Data\CVDLib\AllegroLib\Pad\

------ Summary Statistics ------

netrev run on Sep 26 22:00:07 2011
   DESIGN NAME : 'CVD_IT'
   PACKAGING ON Aug 16 2010 13:46:04

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

 No error detected
 No oversight detected
  1 warnings detected

cpu time      0:03:02
elapsed time  0:00:01

----------------------------------------------------------------------------------------

修正Package即可place元件了