解决混合仿真情况下,Verilog编译,总是说库是在另外一个库编译的,请增加到cds.lib文件里面这个错误

分类: 工作相关 |
I'm here again with my weird errors :P
I have a testbench written in Verilog. Usually, when you save
you
should have in the same Cell View a Symbol (automatically
generated).
In my case, I'm not bale to obtain this because I receive this error:
ncvlog: *F,DLIORG: Library (physical path)
/user/fzappon/testIC6/
Francesco was originally compiled with logical name 'Sinan'.
Please
include the original definition of library in cds.lib file.
and, obviously, I have no Symbol view.
What I've tried to do is: go to Virtuoso main window, select
IBM_PDK --
> Library --> Edit cds.lib file: in this file, the old
library (Sinan)
is defined, so I can't see where the problem could be. Moreover,
I
have the library in my library manager.
Do you have any idea of what this problem could be?
Thanks, as usual, in advance
Francesco.
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Its been a while since Ive seen this error but pretty sure there is
a
library hook in your verilog, try searching for Sinan or library
(not
sure
of the case) then comment it out.
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Francesco,
In your library directory, there will be an outdated "pak" file. Something like
inca.lnx86.165.pak
(there may be more than one).
Please delete the pak files.
If a library is renamed, the pak file remains, but contains
information about
the old library name. As a result, when ncvlog tries to compile the
verilog code
(needed to analyse it to identify pin names and so on), it can't
because there's
a mismatch between the logical name (Sinan, which is what the
library was
previously called, presumably) and the current name
(Francesco?).
Regards,
Andrew.