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VHDL设计4位二进制记数器

(2007-11-25 10:28:28)
标签:

知识/探索

vhdl程序

分类: 程序设计
4位二进制记数器cnt4e.vhd源程序:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY cnt4e IS
    PORT(clk,ena:IN STD_LOGIC;
         cout:OUT STD_LOGIC;
         q:BUFFER INTEGER RANGE 0 TO 15);
END cnt4e;
ARCHITECTURE one OF cnt4e IS
BEGIN
   PROCESS(clk,ena)
   BEGIN
       IF clk 'EVENT AND clk='1' THEN
         IF ena='1' THEN
            IF q=15 THEN q<=0;
                  cout<='0';
              ELSIF q=14 THEN q<=q+1;
                     cout<='1';
             ELSE q<=q+1;
             END IF;
           END IF;
           END IF;
     END PROCESS;
END one;
 

七段显示译码器Dec7s.vhd源程序:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Dec7s IS
            PORT(a:IN BIT_VECTOR(3 DOWNTO 0);
              led7s:OUT BIT_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE one OF Dec7s IS
BEGIN
     PROCESS(A)
       BEGIN
         CASE A(3 DOWNTO 0)IS

           WHEN"0000"=>LED7S<="00111111";
           WHEN"0001"=>LED7S<="00000110";
           WHEN"0010"=>LED7S<="01011011";
           WHEN"0011"=>LED7S<="01001111";
           WHEN"0100"=>LED7S<="01100110";
           WHEN"0101"=>LED7S<="01101101";
           WHEN"0110"=>LED7S<="01111101";
           WHEN"0111"=>LED7S<="00000111";
           WHEN"1000"=>LED7S<="01111111";
           WHEN"1001"=>LED7S<="01101111";
           WHEN"1010"=>LED7S<="01110111";
           WHEN"1011"=>LED7S<="01111100";
           WHEN"1100"=>LED7S<="00111001";
           WHEN"1101"=>LED7S<="01011110";
           WHEN"1110"=>LED7S<="01111001";
           WHEN"1111"=>LED7S<="01110001";
           WHEN OTHERS=>NULL;
        END CASE;
      END PROCESS;
END one;

 

原理图:

VHDL设计4位二进制记数器

 

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