最后的结果就是 compile（编译）成了CLKBUFF,然后我想将这个信号给到FPGAIO185，不成功！

http://s12/mw690/006puSeyzy7a8nuoI9J4b&690global resource AND clkbuf" TITLE="quadrant global resource AND clkbuf" />
感觉：IO185不适合于CLKBUF

不明觉厉！今天下午很悲哀，每个看了都不懂。

粗略看了下，这个问题有点无解

------------------------------------前记---------------------------------------

Design Constraints Overview

Design constraints are usually either requirements or properties in your design. You use constraints to ensure that your design meets its performance goals and pin assignment requirements.

The Designer software supports both timing and physical constraints. In addition, it supports netlist optimization constraints. You can set constraints by either using Actel's interactive tools or by importing constraint files directly into your design session.

Physical Constraints

Designer software enables you to specify the physical constraints to define the size, shape, utilization, and pin/pad placement of a design. You can specify these constraints based on the utilization, aspect ratio, and dimensions of the die. The pin/pad placement depends on the external physical environment of the design, such as the placement of the device on the board.

There are three types of physical constraints:

• I/O assignments

- Set location, attributes, and technologies for I/O ports

- Specify special assignments, such as VREF pins and I/O banks

• Location and region assignments

- Set the location of Core, RAM, and FIFO macros

- Create Regions for I/O and Core macros as well as modify those regions

• Clock assignments

- Assign nets to clocks

- Assign global clock constraints to global, quadrant, and local clock resources

----------------------------感觉这就是我要找的------------------------------------------keep on

受到物理逻辑约束后 综合成了 clkbuf,那CLKBUF是什么，为什么要被综合成这个？

1.CLKBUF： 一种类型的macro cell（双向端口bibuf，输入端口inbuf,输出端口outbuf,高阻态(3态门)：tribuff）

特用于高扇出、时钟网络等有一定要求的信号。

2. satisfy the clock network resource constraints，就是说它认为你这个信号，跟时钟差不多了，所以他要更好的利用FPGA的资源，就用了一个CLKBUF，这种macro在一个FPGA的资源表中不多，仅仅只有6个！

----------------------------------------------------------------

Physical Constraints for Quadrant Clocks

If quadrant clocks are present in a design or if it is necessary to “promote” global clocks (CLKBUF, CLKINT, PLL, CLKDLY) to quadrant clocks to satisfy the clock network resource constraints, you must define physical design constraints to execute the promotion. You may choose to create physical design constraints using PDC commands (pre-compile) or the MVN interface (post-compile).

 

The advantage of using the PDC flow over the MVN flow is that Compile is able to automatically promote any regular net to a global net before assigning it to a quadrant.

-----------------------------------------------------------------------理解

global clocks:全局时钟所使用的macro cell类型（CLKBUF、CLKINT、PLL、CLKDLY）

你可以定义物理设计约束来执行这个优化，定义物理设计约束可以通过PDC commands 或者 MVN 接口完成，但PDC流

------------------------------------------------------------

现在可以回答为什么，我赋值FPGAIO185到CLKBUF不成功了

--------------如下

Prelayout Physical Constraint Verification

The prelayout checker performs the following DRC (Design Rule Checker) checks:

• The remaining clocks, which need to be assigned to a global clock resource, need to be less than 6.  For example:

Resource Limit

The number of chip globals in your design exceeded the maximum number

available in the device.

• The checker verifies that the total number of clock resources assigned to the given quadrant does not exceed 3.  For example:

PRL09: The number of clocks assigned (4) to the Upper Left quadrant exceeds the maximum number available (3) in the device.

• If a clock is placed and assigned to a quadrant clock region, the checker verifies that the clock is placed in the given quadrant clock region.  For example:

PRL11: Cannot assign net:net_out2 to the Upper Right quadrant and its driver macro:clkbibuf1 to Upper Left quadrant which is outside the quadrant.

因为在布局布线的时候，他有一个 Prelayout Physical Constraint Verification

这个会检查上面规则

1.global clock resource less than 6

时钟网络信号是否少于6个

2.给予的CLOCK所处象限是否高于3

小结：FPGA的IO在一定的功能区内，可以任意赋值，但内部的资源分布是有区别的，不同的功能属性区域只能用于特定的IO。说白了，就是IO185,不用于CLKBUF的属性。

---------------------------------------------------------------------

问题1：那我怎么知道FPGA内部的那些口是哪些资源特性呢？（比如具备CLKBUF的IO有哪些）

问题2：我如何将一个信号的需求macro cell类型，赋值或者改变

------------------------------------------------------------------------

问题1：估计看具体芯片的datasheet可以找到答案，这里先不回答。

解决问题2：如何定义一个信号的macro cell类型

------一下为解决问题2而生---------专用分界线--------------------------------

You may choose to create physical design constraints using PDC commands (pre-compile) 

问题来了，PDC commands是个什么东西，咋个使用呢？

A PDC file is a Tcl script file specifying physical constraints. This file can be imported and exported from Designer. Any constraint that you can enter using the PinEditor in MVN or ChipPlanner tool, you can also use in a PDC file.

继续查看PDC文件

http://s14/mw690/006puSeyzy7aa54SXCd9d&690global resource AND clkbuf" TITLE="quadrant global resource AND clkbuf" />

这里都是添加

----------------------------------发现有点不对 走偏了 ---------------------------------

因为在我这里，我是想让他直接不生成CLKBUF,但由于高扇出，系统在编译的时候直接将一个普通的信号网络，编译成了CLKBUF的macro cell.

---------------------------继续看看 编译配置选项----------------------

http://s10/mw690/006puSeyzy7aa4JPfNn69&690global resource AND clkbuf" TITLE="quadrant global resource AND clkbuf" />

将红色卡框内的数据设置大一点 20

再次IO 特性管理

http://s8/mw690/006puSeyzy7aa5cU6nta7&690global resource AND clkbuf" TITLE="quadrant global resource AND clkbuf" />

成功！