分类: 工作学习 |
(1)正常计时模块clock
module clock(clk,rst,clock_en,second,minute,hour);
input clk,rst,clock_en;
output[5:0]second,minute,hour;
reg[5:0]second,minute,hour;
always@(posedge clk or negedge rst or posedge clock_en)
if(!rst)
begin
second<=0;
end
else if(clock_en)