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版图英文翻译

(2011-03-12 01:12:02)
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杂谈

分类: 版图方面

General Guidelines 

总原则

This section describes the models the software uses and gives you some general tips on the best ways to model the cells in your library.

本部分介绍模型,给你一些软件常规的使用方法,让你以最佳的方式在媒体库中单元建模。

General Rules for All Cell Types

对所有单元类型的总规则

Every logical pin must have a physical description that contains at least one port. Each port must have at least one physical geometry.

每个电路引脚都必须有一个物理描述,这个描述包含一个以上的端口。每个端口必须至少有一个物理图形。

All objects belonging to the cell must be inside the cell boundary.

在单元内部所有的金属线都必须有单元边界。

In some technologies, power and ground pins extend to the edge or outside the boundary.

在有些技术上,电源和接地引脚会伸出到边界或者边界外面。

The edges of pins and blockages must be at least one half the minimum spacing away from the cell boundary.

引脚的边缘和阻挡层必须至少有半数的最小间距离开单元的边界。

Minimizing cell size does not necessarily minimize die size. It is better to increase the cell size slightly to optimize routing than to minimize cell size without keeping routing considerations in mind.

减少单元尺寸并不一定能减少芯片尺寸,稍微增加单元尺寸比刻意减小单元尺寸的布线来得好。

Designing Standard Cells    

设计标准单元

This section provides suggestions for optimizing your design at the library level or inter-cell level, to ensure that the individual cells work together as well as possible.

本节提供优化单元库和INTER-CELL水平设计建议,为了确保单个的单元在一起能工作的更好。

Optimize Cell Widths   

优化单元宽度

Avoid creating standard cells of the same type that vary greatly in width.

同意类型的标准单元避免宽度变化过大。

This results in unbalanced row lengths. In general, the width of the largest standard cells should be no more than five or six times the width of smallest standard cell of the same type in your library.

单元变化过大会导致行的长度不平衡。一般来说,在你的单元库中相同类型的最大宽度标准单元不应超过最小标准单元宽度的5到6倍。

If you need more complex cells, it is better to double or triple the height of the cells and keep a reasonable cell width. Silicon Ensemble can optimize the area utilization by mixing single- and multiple-height cells in the core area without creating gaps around multiple-height cells.

如果你需要更复杂的单元,最好是单元高度的2到3倍,并且要保持一个合理的单元宽度。自动布局布线工具能通过混合单倍和多倍高度来优化围绕着多倍高度的没有缝隙的中心区域。

All cell widths should be a multiple of the pin grid.

所有单元必须是PITCH的倍数。

If a cell width is not a multiple of the pin grid, even though its pins are on the grid, the cell will cause the cells adjacent to it to be misaligned with respect to the grid. This makes having pins on grid useless because the misalignment of the other cells causes their pins to be off-grid, thereby using more horizontal or vertical tracks than needed.

如果一个单元宽度不是PITCH的倍数,即使它在引脚的网格点上,也会导致邻近的单元在网格上不对齐。这些使得网格上的引脚没有用,因为其他不重合的单元导致他们的引脚偏离网格,从而要更多使用水平或垂直轨线。

Making the cell width a multiple of the pin grid can increase the size of the cell, but will yield a reduction in the total area of the die.

使单元宽度为PITCH的倍数能增加单元尺寸,但是能减少整体芯片的尺寸。

Placement should also be done on a placement snap grid so that the edges of the cells are also on the grid.

布局也应该放置在一个捕捉栅格位置以便边缘的单元格同样能在网格上。

Optimize Cell Heights

优化单元高度

Optimal cell heights vary depending on the row style your design uses.

最佳单元高度取决于你设计的行的类型。

Of the four styles described below, using the second style is highly discouraged. You can use any of the other three for Silicon Ensemble. The last two row styles typically result in the smallest die sizes.

下面介绍四种不同类型的设计。使用第二种类型是不行的,你可以使用其他任何三种自动布局布线工具。最后两种行的类型能使芯片最小。

Style 1: Standard height cells in single cell rows

第一种类型:每个单元的高度是相同的。

Typically, these designs have two or more layers. Cell height is limited. You can have power sharing if you design it in. Power sharing can reduce die size by reducing the number of channels.

通常,这些设计有两或两层以上的层。单元高度是有限制的。你这样设计是可以电源共享的。电源共享能通过减少通道数来减小芯片面积。

Style 2: Variable height cells, in single cell rows

第二种类型:不同高度的单元在单个单元行中。

These designs are usually two-layer designs. They are not very efficient for three or more layers. They allow cell heights to vary by about 30%, but do not allow for power sharing.

这种设计通常是两层的。他们不是三或三层以上的都很有效率。他们的高度可以改变30%,但不允许电源共享。

Style 3: Single-height and double-height cells, in double cell rows

第三种类型:单一高度和双重高度的单元在双重单元行里

These designs have two or more layers. Single-height or double-height cells are arranged in double rows. This kind of design is meant for power sharing.

这种设计有两层或两层以上。单倍和双倍高度的单元行被排列在双倍单元行中。这种设计也是单元共享的。

Style 4: Multi-height cells in a sea-of-cells design

第四种类型:多倍高度单元在门海法中使用

These designs feature three or more layers. They do not allow two-layer routing and have no channels, so you cannot use a channel-based router. You can have single-, double-, or multi-height cells. This kind of design permits the most efficient power sharing of both power lines.

这些设计结构的特点是用三个或三个以上的层。他们不允许两层布线并且没有通道,因此你不能用一个基于通道的布线器。你能用单一的,双层的,或者多种高度的单元。这种类型的设计是通过电源共享达到最高效率的。

Optimize Porosity

优化孔隙度

Medium and large cells should have the same porosity, primarily in M2.

中型和大型单元都有相同的孔隙度,主要都是在M2层。

This means that the percentage of free M2 tracks should be the same for all the medium and large cells in the library. If the porosity is not uniform, the router might have trouble finishing if cells with low porosity are placed near each other.

这意味着空闲M2的比例应该和库里的所有的中型的和大型的单元一样。如果孔隙度不是统一的,如果低孔隙度防止在彼此相邻的位置,布线会很难完成。

For small cells (one to three tracks wide) you can generally let the placer optimize porosity by spacing them apart where necessary. However, careful design can improve routability significantly.

对于小单元(一到三轨线宽度的)通常,你能让布线器通过分开pin来优化孔隙度。然而,精心设计能显著提高布线率。

For example, you can maximize M1 left/right access to pins on small cells, as shown in the following figure. This optimizes M2 porosity by maximizing the amount of routing done on M1. Small cells often have this kind of routing.

例如,在小单元上你可以最大限度的发挥M1左/右来接近引脚,如下图所示。通过最大化M1上的数量来优化M2层上的孔隙度。小单元常常用这种类型的工艺。

You can also design small cells to have multiple accessible pins or open grids so that you can get Z-shape M2 routes where possible, as shown in the following example.

你也可以设计小单元拥有多个可连接的引脚或开放式轨线,这样你就可以走Z线形的M2线路,如接下来的几种例子。

Designing Pins for Cells

设计单元引脚

This section contains guidelines for designing pins so that you maximize the routability of the cells and improve the run time and memory performance of the router. The more porous the design, the easier it is for the router to make connections.

本部分包含设计指南,关于设计引脚的,这样你能最大限度提高单元布线很提高运行时间和布线器的记忆功能。更多孔设计就最容易让布线器连接。

Placing Pins on the Grid

把引脚放在网格上

Every pin should cover at least one grid intersection, because the software connects most efficiently to pins at grid intersections. If you have off-grid pins, the software creates a pseudogrid through the center of each off-grid pin. Use the following guidelines to optimize pin placement:

每个引脚应该覆盖至少一个网格交叉点,由于软件连接最有效的是引脚在网格交叉点上。如果你的引脚是脱离网格的,就可以通过该中心每个离网的引脚来创造一个虚拟轨线。使用下列的指导来优化引脚放置:

Place pins on-grid wherever possible.

尽可能让引脚在网格上。

Ensure that off-grid pins follow spacing rules, using the pseudogrid point at the center of the pin geometry.

确保非网格的引脚遵循空间规则,利用虚拟网格贯穿引脚图形的中心。

Center the pin via on the routing grid for its layer.

把引脚的通孔放在布线轨线的中心上。

Place special pins so that they do not obstruct routing on an adjacent track. You can place special pins off-grid for this.

放置特殊引脚时,要让他们不要妨碍相邻通道的布线,你能把特殊引脚放置在离网格上。

Silicon Ensemble has gridless routers, but they handle gridded pins better than off-grid pins. A pin is on-grid if

自动布局布线工具有非网格布线器,但他们处理网格引脚比非网格引脚好。如果一个引脚在网格上的条件:

The pin rectangle is centered at the grid intersection.

引脚矩形的中心在网格点上。

The pin rectangle encloses the grid intersection point on all four sides by half the minimum metal width of that pin shape layer. The grid intersection is from the x and y routing grid pitch for that layer. The router routes to the pin rectangle only at that grid intersection.

引脚围绕网格交叉点成矩形,在引脚图层通过最小金属宽度的一半指向所有四边。在网格交叉点上是通过图层工艺网格的X和Y轴。布线器把引脚布线在网格交叉点上。

The router only routes to the center of off-grid pin port rectangles, if this is legal.

如果这是合规矩的,布线器就布线到非网格交叉点的中心。

The following figure shows a LEF standard cell with shapes similar to layout data.

下面的图展示了LEF标准单元和形状类似的布局数据。

Pin A has several off-grid shapes and one on-grid shape. Pin B has two off-grid polysilicon pin shapes. Pin O has one on-grid shape. The off-grid shapes slow down the router and lead to inefficient routing. Further, if the spacing rules for this example did not allow M1/M2 vias to be placed on pin A, the router would not be able to connect to Pin A easily. This could result

in an inefficiently routed design.

引脚A有多个非网格形状和一个网格图形。引脚B有两个非网格多晶硅材料的引脚图形。引脚O是一个在网格的图形。非网格图形减慢了布线器的布线速度和导致布线效率降低。另外,如果尺寸规则不允许M1/M2的通孔放置在引脚A上,那么布线器就不能很容易的连接上引脚A,这会导致一个低效率的布线设计。

Off-grid pins can affect your design in a number of ways:

非网格引脚将会在多个方面影响你的设计:

Larger die size

更大的芯片尺寸

The router creates jogs to compensate for pins that are not aligned. This forces the channels to expand vertically and increases the die size.

布线器为没有对齐的引脚创建直角走线来弥补,直角走线强迫了通道在垂直方向上扩大并且增大芯片尺寸。

Overconstrained design

过多阻挡层的设计

The more constraints there are, the harder it is for the router. The following figure shows how one off-grid pin increases the number of constraints.

如果你阻挡层越多,布线越困难。下面这张插图表示了一个非网格点引脚是如何增加阻挡层的数目。

Longer run-times

过长的运行时间

This design slows down the router significantly because the router is more constrained.

这个设计减慢了布线器的布线速度,因为布线器会有很多阻挡层。

Each off-grid track can interfere with adjacent tracks.

每个非格点轨线干扰到邻近轨线。

Optimistic global router results

盲目乐观地全局布线结果

The global router might not recognize off-grid pins as blocking the routing track and, as a result gives you optimistic results.

全局布线器不会把非格点引脚看成是阻挡层,这样导致你有一个过度乐观的设计结果。

Handling Special Pins

处理特殊引脚

Special pins are pins routed by the special net router instead of the final router. Special pins have different shapes, depending on their function. On cells, you can have feedthrough or abutment special pins.

用特殊结点布线器代替最终布线器来布特殊引脚的线,根据它的特殊功能,特殊引脚有不同的图形。在单元里,你可以贯穿或拼接特殊引脚。

Non-interference with adjacent grid lines.

不要干扰邻近的格点轨线

Define special pins in the SPECIAL NETS section of the DEF file.

DEF里的特殊格点会定义特殊引脚。

Place all power and ground feedthrough and abutment pins at the same axis on opposite sides of the cell.

把在相同轴线的贯穿和拼接的电源和接地引脚对称放置。

Position the power and ground feedthrough or abutment pins so that they align with corresponding pins in other cells.

要把电源和接地的引脚贯穿放置以便于电源和地对齐。

Avoid creating power and ground pins in M2, because M2 within the cell makes it harder to route over the cell.

避免用M2做电源和地的引脚,因为M2很难在单元里布线。

Define a shape property for power and ground pins with the value set to either feedthru or abutment.

我们要把电源和地的引脚定义为贯穿和拼接放置的。

Set the same y offset for power and ground pins from the cell origin so that the FollowPins command works properly. You can specify the origin in the LEF file or use the default, which is the lower left corner.

电源的引脚和地的引脚距离原点的偏移量必须相同。你可以指定源LEF文件或使用默认的原点。

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